1. Field of the Invention
The present invention relates to a ferroelectric memory, for example, to a refresh operation in the ferroelectric memory.
2. Background Art
A ferroelectric memory is a semiconductor memory including a ferroelectric capacitor as a component of a memory cell. In general, the memory cell in the ferroelectric memory includes the ferroelectric capacitor and a cell transistor.
In general, the ferroelectric memory is provided with lines such as word lines, bit lines, and plate lines. In the ferroelectric memory, if the word lines are not associated with the plate lines in one-to-one correspondence, charges stored at a node between the ferroelectric capacitor and the cell transistor poses a problem. The stored charges and their leak become a cause of reliability lowering of the ferroelectric memory.
In a conventional ferroelectric memory, a refresh operation of turning on a word line to release the charges is performed periodically as a measure to counter this problem. However, when performing the refresh operation, it is necessary that the plate line and the bit line have the same potential. Therefore, in the conventional art, the refresh operation cannot be performed in situations where accesses for reading and/or writing are performed frequently.
JP-A 2000-11665 (KOKAI) describes an example of a ferroelectric memory which performs a data reading operation to read binary data from a selected cell, a counter data writing operation to write data which is opposite in a logical level to the read binary data into the selected cell, and an identical data writing operation to write data which is identical in a logical level as the read binary data into the selected cell again, as a sequential refresh operation.